Generally, when a semiconductor device is manufactured, various processes such as a film forming process, a pattern etching process and the like are repeatedly performed on a semiconductor wafer to manufacture a desired device. With a demand for high integration and high miniaturization of semiconductor devices, a line width and a hole diameter are getting smaller. Further, as for a wiring material or a filling material for filling a recess such as a trench, a hole or the like, there has been a tendency of using copper (Cu) which has a significantly low electric resistance and is inexpensive to satisfy the need to reduce electrical resistance due to the miniaturization of various dimensions (Japanese Patent Application Publication No. 2004-107747). When copper is used as the wiring material or the filling material, a tantalum (Ta) metal film, a tantalum nitride (TaN) film or the like is generally used as a barrier layer in consideration of a diffusion barrier property for copper to the underlying layers.
In order to fill the recess with copper, a thin seeding film formed of a copper film is firstly formed on the entire wafer surface including the entire inner surface of the recess by using a plasma sputtering apparatus. Then, a copper plating process is performed on the entire wafer surface, so that the inside of the recess is completely filled. Thereafter, the excessive copper thin film on the wafer surface is removed by a polishing process such as a CMP (chemical mechanical polishing) process or the like.
This will be described with reference to FIGS. 13A to 13C. FIGS. 13A to 13C show a conventional process for filling a recess of a semiconductor wafer. A recess 2, e.g., a via hole, a through hole or a groove (a trench), having a single damascene structure, a dual damascene structure or a three-dimensional mounting structure is formed on a surface of an insulating layer 1, e.g., an interlayer insulation film constituted of a SiO2 film, formed on the semiconductor wafer W. At the bottom of the recess 2, an underlying wiring layer 3 made of, e.g., copper, is formed to be exposed.
Specifically, the recess 2 includes a thin and long groove (trench) 2A and a hole 2B formed at a part of the bottom portion of the groove 2A and serving as a via hole or a through hole. Further, the wiring layer 3 is exposed on the bottom portion of the hole 2B to make electric connection to an underlying wiring layer or a device such as a transistor or the like. The illustration of the underlying wiring layer or the device such as a transistor or the like is omitted. Due to the miniaturization of design rules, the recess 2 has a very small width or inner diameter of, e.g., about 120 nm, and an aspect ratio of, e.g., about 2 to 4. The illustration of a diffusion barrier film, an etching stop film or the like is simplified or omitted.
A barrier layer 4 having, e.g., a laminated structure of a TaN film and a Ta film, has been substantially uniformly formed beforehand on the surface of the semiconductor wafer W including the inner surface of the recess 2 by using a plasma sputtering apparatus (see FIG. 13A). Then, a seeding film 6 formed of a thin copper film as a metal film is formed on the entire surface of the wafer including the inner surface of the recess 2 by using the plasma sputtering apparatus (see FIG. 13B). Thereafter, a copper plating process is performed on the wafer surface, so that the recess 2 is filled with a metal film 8 formed of, e.g., a copper film (see FIG. 13C). Next, the excessive metal film 8, the excessive seeding film 6 and the excessive barrier layer 4 on the wafer surface are removed by a polishing process such as the CMP process or the like.
Various developments have been made in order to further improve the reliability of the barrier layer. Among them, a self-forming barrier layer using a Mn film or a CuMn alloy film instead of the Ta film and the TaN film attracts attention (Japanese Patent Application Publication No. 2005-277390). The Mn film or the CuMn alloy film is formed by sputtering. Further, the Mn film or the CuMn alloy film itself serves as a seeding film, so that a Cu plating layer can be formed directly thereon. Since an annealing process is performed after the plating process is completed, the film reacts with a SiO2 layer as a lower insulation film in a self-aligned manner. Thus, a barrier film such as a MnSixOy (x and y being any integers) film or manganese oxide MnOx (x being any integers) obtained by reaction between Mn and oxygen in the SiO2 layer is formed at a boundary portion between the SiO2 layer and the Mn film or the CuMn alloy film. Accordingly, the number of production processes can be reduced. The manganese oxide includes MnO, Mn3O4, Mn2O3, MnO2 and the like depending on the valency of the Mn. They are generally referred to as “MnOx” in this specification. Moreover, there is studied a technique for forming a MnSixOy film or a MnOx film by a CVD method capable of depositing a film with a good step coverage for a fine line width or hole diameter compared to a sputtering method (Japanese Patent Application Publication No. 2008-013848).
Meanwhile, along with a recent demand for high-speed operations of semiconductor devices, a relative dielectric constant of the interlayer insulation film needs to be further decreased. Due to this demand, it is suggested to use, as a material of the interlayer insulation film, a silicon oxide film made of TEOS or a low-k film made of a material having a lower relative dielectric constant such as SiOC, SiCOH or the like containing an organic group, e.g., a methyl group. Here, the relative dielectric constant of the silicon oxide film made of TEOS is about 4.1, and the relative dielectric constant of SiOC is about 3.0. However, when the low-k film is used as the interlayer insulation film, a MnOx film is hardly deposited even though a Mn-containing film forming process is performed by a CVD method on the surface of the interlayer insulation film having a low relative dielectric constant which includes the exposed surface in the recess. As a result, a barrier layer cannot be formed.